GSIT » Topics » Manufacturing

These excerpts taken from the GSIT 10-K filed Jun 10, 2009.

Manufacturing

        We outsource our wafer fabrication, assembly and a significant portion of our testing, which enables us to focus on our design strengths, minimize fixed costs and capital expenditures and gain access to advanced manufacturing technologies. Our engineers work closely with our outsource partners to increase yields, reduce manufacturing costs, and help assure the quality of our products.

        Currently, all of our wafers are manufactured by TSMC under individually negotiated purchase orders. We do not currently have a long-term supply contract with TSMC, and therefore, TSMC is not obligated to manufacture products for us for any specified period, in any specified quantity or at any specified price, except as may be provided in a particular purchase order. Our future success depends in part on our ability to secure sufficient capacity at TSMC or other independent foundries to supply us with the wafers we require.

        Most of our products are implemented using 0.13 micron and 90 nanometer process technologies on 300 millimeter wafers using process technology developed by TSMC. We currently have five separate product families in production using the 0.13 micron process. Our 72 megabit SigmaQuad, 72 megabit synchronous BurstRAM and NBT SRAM and our 36 megabit SigmaQuad products are currently manufactured using 90 nanometer process technology. We are also developing new synchronous SRAMs using 65 nanometer process technology.

        Our master die methodology enables multiple product families, and variations thereof, to be manufactured from a single mask set. As a result, based upon the way available die from a wafer are metalized, wire bonded, packaged and tested, we can create a number of different products. The manufacturing process consists of two phases, the first of which takes approximately eight to twelve

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weeks and results in wafers that have the potential to yield multiple products within a given product family. After the completion of this phase, the wafers are stored pending customer orders. Once we receive orders for a particular product, we perform the second phase, consisting of final wafer processing, assembly, burn-in and test, which takes approximately six to ten weeks to complete. This two-step manufacturing process enables us to significantly shorten our product lead times, providing flexibility for customization and to increase the availability of our products.

        All of our manufactured wafers are tested for electrical compliance and most are packaged at Advanced Semiconductor Engineering, or ASE, which is located in Taiwan. Our test procedures require that all of our products be subjected to accelerated burn-in and extensive functional electrical testing, a significant portion of which occurs at Sigurd Microelectronics Co. and King Yuan Electronics Company. We perform testing for most of our low volume products in-house at our Santa Clara, California and our Taiwan facilities and continue to transition final test away from outside test houses to our Taiwan facility.

Manufacturing

        We outsource our wafer fabrication, assembly and a significant portion of our testing, which enables us to focus on our design strengths, minimize fixed costs and capital expenditures and gain access to advanced manufacturing technologies. Our engineers work closely with our outsource partners to increase yields, reduce manufacturing costs, and help assure the quality of our products.

        Currently, all of our wafers are manufactured by TSMC under individually negotiated purchase orders. We do not currently have a long-term supply contract with TSMC, and therefore, TSMC is not obligated to manufacture products for us for any specified period, in any specified quantity or at any specified price, except as may be provided in a particular purchase order. Our future success depends in part on our ability to secure sufficient capacity at TSMC or other independent foundries to supply us with the wafers we require.

        Most of our products are implemented using 0.13 micron and 90 nanometer process technologies on 300 millimeter wafers using process technology developed by TSMC. We currently have five separate product families in production using the 0.13 micron process. Our 72 megabit SigmaQuad, 72 megabit synchronous BurstRAM and NBT SRAM and our 36 megabit SigmaQuad products are currently manufactured using 90 nanometer process technology. We are also developing new synchronous SRAMs using 65 nanometer process technology.

        Our master die methodology enables multiple product families, and variations thereof, to be manufactured from a single mask set. As a result, based upon the way available die from a wafer are metalized, wire bonded, packaged and tested, we can create a number of different products. The manufacturing process consists of two phases, the first of which takes approximately eight to twelve

11


Table of Contents


weeks and results in wafers that have the potential to yield multiple products within a given product family. After the completion of this phase, the wafers are stored pending customer orders. Once we receive orders for a particular product, we perform the second phase, consisting of final wafer processing, assembly, burn-in and test, which takes approximately six to ten weeks to complete. This two-step manufacturing process enables us to significantly shorten our product lead times, providing flexibility for customization and to increase the availability of our products.

        All of our manufactured wafers are tested for electrical compliance and most are packaged at Advanced Semiconductor Engineering, or ASE, which is located in Taiwan. Our test procedures require that all of our products be subjected to accelerated burn-in and extensive functional electrical testing, a significant portion of which occurs at Sigurd Microelectronics Co. and King Yuan Electronics Company. We perform testing for most of our low volume products in-house at our Santa Clara, California and our Taiwan facilities and continue to transition final test away from outside test houses to our Taiwan facility.

Manufacturing



        We outsource our wafer fabrication, assembly and a significant portion of our testing, which enables us to focus on our design
strengths, minimize fixed costs and capital expenditures and gain access to advanced manufacturing technologies. Our engineers work closely with our outsource partners to increase yields, reduce
manufacturing costs, and help assure the quality of our products.



        Currently,
all of our wafers are manufactured by TSMC under individually negotiated purchase orders. We do not currently have a long-term supply contract with TSMC, and
therefore, TSMC is not obligated to manufacture products for us for any specified period, in any specified quantity or at any specified price, except as may be provided in a particular purchase order.
Our future success depends in part on our ability to secure sufficient capacity at TSMC or other independent foundries to supply us with the wafers we require.



        Most
of our products are implemented using 0.13 micron and 90 nanometer process technologies on 300 millimeter wafers using process technology developed by TSMC. We currently have five
separate product families in production using the 0.13 micron process. Our 72 megabit SigmaQuad, 72 megabit synchronous BurstRAM and NBT SRAM and our 36 megabit SigmaQuad products are currently
manufactured using 90 nanometer process technology. We are also developing new synchronous SRAMs using 65 nanometer process technology.



        Our
master die methodology enables multiple product families, and variations thereof, to be manufactured from a single mask set. As a result, based upon the way available die from a
wafer are metalized, wire bonded, packaged and tested, we can create a number of different products. The manufacturing process consists of two phases, the first of which takes approximately eight to
twelve



11









HREF="#bg78801a_main_toc">Table of Contents






weeks
and results in wafers that have the potential to yield multiple products within a given product family. After the completion of this phase, the wafers are stored pending customer orders. Once we
receive orders for a particular product, we perform the second phase, consisting of final wafer processing, assembly, burn-in and test, which takes approximately six to ten weeks to
complete. This two-step manufacturing process enables us to significantly shorten our product lead times, providing flexibility for customization and to increase the availability of our
products.



        All
of our manufactured wafers are tested for electrical compliance and most are packaged at Advanced Semiconductor Engineering, or ASE, which is located in Taiwan. Our test procedures
require that all of our products be subjected to accelerated burn-in and extensive functional electrical testing, a significant portion of which occurs at Sigurd
Microelectronics Co. and King Yuan Electronics Company. We perform testing for most of our low volume products in-house at our Santa Clara, California and our Taiwan facilities and
continue to transition final test away from outside test houses to our Taiwan facility.




Manufacturing



        We outsource our wafer fabrication, assembly and a significant portion of our testing, which enables us to focus on our design
strengths, minimize fixed costs and capital expenditures and gain access to advanced manufacturing technologies. Our engineers work closely with our outsource partners to increase yields, reduce
manufacturing costs, and help assure the quality of our products.



        Currently,
all of our wafers are manufactured by TSMC under individually negotiated purchase orders. We do not currently have a long-term supply contract with TSMC, and
therefore, TSMC is not obligated to manufacture products for us for any specified period, in any specified quantity or at any specified price, except as may be provided in a particular purchase order.
Our future success depends in part on our ability to secure sufficient capacity at TSMC or other independent foundries to supply us with the wafers we require.



        Most
of our products are implemented using 0.13 micron and 90 nanometer process technologies on 300 millimeter wafers using process technology developed by TSMC. We currently have five
separate product families in production using the 0.13 micron process. Our 72 megabit SigmaQuad, 72 megabit synchronous BurstRAM and NBT SRAM and our 36 megabit SigmaQuad products are currently
manufactured using 90 nanometer process technology. We are also developing new synchronous SRAMs using 65 nanometer process technology.



        Our
master die methodology enables multiple product families, and variations thereof, to be manufactured from a single mask set. As a result, based upon the way available die from a
wafer are metalized, wire bonded, packaged and tested, we can create a number of different products. The manufacturing process consists of two phases, the first of which takes approximately eight to
twelve



11









HREF="#bg78801a_main_toc">Table of Contents






weeks
and results in wafers that have the potential to yield multiple products within a given product family. After the completion of this phase, the wafers are stored pending customer orders. Once we
receive orders for a particular product, we perform the second phase, consisting of final wafer processing, assembly, burn-in and test, which takes approximately six to ten weeks to
complete. This two-step manufacturing process enables us to significantly shorten our product lead times, providing flexibility for customization and to increase the availability of our
products.



        All
of our manufactured wafers are tested for electrical compliance and most are packaged at Advanced Semiconductor Engineering, or ASE, which is located in Taiwan. Our test procedures
require that all of our products be subjected to accelerated burn-in and extensive functional electrical testing, a significant portion of which occurs at Sigurd
Microelectronics Co. and King Yuan Electronics Company. We perform testing for most of our low volume products in-house at our Santa Clara, California and our Taiwan facilities and
continue to transition final test away from outside test houses to our Taiwan facility.




These excerpts taken from the GSIT 10-K filed Jun 17, 2008.

Manufacturing

        We outsource our wafer fabrication, assembly and a significant portion of our testing, which enables us to focus on our design strengths, minimize fixed costs and capital expenditures and gain access to advanced manufacturing technologies. Our engineers work closely with our outsource partners to increase yields, reduce manufacturing costs, and help assure the quality of our products.

        Currently, all of our wafers are manufactured by TSMC under individually negotiated purchase orders. We do not currently have a long-term supply contract with TSMC, and therefore, TSMC is not obligated to manufacture products for us for any specified period, in any specified quantity or at any specified price, except as may be provided in a particular purchase order. Our future success depends in part on our ability to secure sufficient capacity at TSMC or other independent foundries to supply us with the wafers we require.

        Most of our products are implemented using 0.13 micron and 90 nanometer process technologies on 300 millimeter wafers using process technology developed by TSMC. We currently have five separate product families in production using the 0.13 micron process. Our 72 megabit SigmaQuad, 72 megabit synchronous BurstRAM and NBT SRAM and our 36 megabit SigmaQuad products are currently manufactured using 90 nanometer process technology. We are also developing new synchronous SRAMs using 65 nanometer process technology.

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        Our master die methodology enables multiple product families, and variations thereof, to be manufactured from a single mask set. As a result, based upon the way available die from a wafer are metalized, wire bonded, packaged and tested, we can create a number of different products. The manufacturing process consists of two phases, the first of which takes approximately eight to twelve weeks and results in wafers that have the potential to yield multiple products within a given product family. After the completion of this phase, the wafers are stored pending customer orders. Once we receive orders for a particular product, we perform the second phase, consisting of final wafer processing, assembly, burn-in and test, which takes approximately six to ten weeks to complete. This two-step manufacturing process enables us to significantly shorten our product lead times, providing flexibility for customization and to increase the availability of our products.

        All of our manufactured wafers are tested for electrical compliance and most are packaged at Advanced Semiconductor Engineering, or ASE, which is located in Taiwan. Our test procedures require that all of our products be subjected to accelerated burn-in and extensive functional electrical testing, a significant portion of which occurs at Sigurd Microelectronics Co. and King Yuan Electronics Company. We perform testing for most of our low volume products in-house at our Santa Clara, California and our Taiwan facilities and continue to transition final test away from outside test houses to our Taiwan facility.

Manufacturing



        We outsource our wafer fabrication, assembly and a significant portion of our testing, which enables us to focus on our design strengths, minimize fixed costs and
capital expenditures and gain access to advanced manufacturing technologies. Our engineers work closely with our outsource partners to increase yields, reduce manufacturing costs, and help assure the
quality of our products.



        Currently,
all of our wafers are manufactured by TSMC under individually negotiated purchase orders. We do not currently have a long-term supply contract with TSMC, and
therefore, TSMC is not obligated to manufacture products for us for any specified period, in any specified quantity or at any specified price, except as may be provided in a particular purchase order.
Our future success depends in part on our ability to secure sufficient capacity at TSMC or other independent foundries to supply us with the wafers we require.



        Most
of our products are implemented using 0.13 micron and 90 nanometer process technologies on 300 millimeter wafers using process technology developed by TSMC. We
currently have five separate product families in production using the 0.13 micron process. Our 72 megabit SigmaQuad, 72 megabit synchronous BurstRAM and NBT SRAM and our
36 megabit SigmaQuad products are currently manufactured using 90 nanometer process technology. We are also developing new synchronous SRAMs using 65 nanometer process technology.



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        Our master die methodology enables multiple product families, and variations thereof, to be manufactured from a single mask set. As a result, based upon the way available die from a
wafer are metalized, wire bonded, packaged and tested, we can create a number of different products. The manufacturing process consists of two phases, the first of which takes approximately eight to
twelve weeks and results in wafers that have the potential to yield multiple products within a given product family. After the completion of this phase, the wafers are stored pending customer orders.
Once we receive orders for a particular product, we perform the second phase, consisting of final wafer processing, assembly, burn-in and test, which takes approximately six to ten weeks
to complete. This two-step manufacturing process enables us to significantly shorten our product lead times, providing flexibility for customization and to increase the availability of our
products.



        All
of our manufactured wafers are tested for electrical compliance and most are packaged at Advanced Semiconductor Engineering, or ASE, which is located in Taiwan. Our test procedures
require that all of our products be subjected to accelerated burn-in and extensive functional electrical testing, a significant portion of which occurs at Sigurd
Microelectronics Co. and King Yuan Electronics Company. We perform testing for most of our low volume products in-house at our Santa Clara, California and our Taiwan facilities and
continue to transition final test away from outside test houses to our Taiwan facility.




This excerpt taken from the GSIT 10-K filed Jun 20, 2007.

Manufacturing

We outsource our wafer fabrication, assembly and a majority of our testing, which enables us to focus on our design strengths, minimize fixed costs and capital expenditures and gain access to advanced manufacturing technologies. Our engineers work closely with our outsource partners to increase yields, reduce manufacturing costs, and help assure the quality of our products.

Currently, all of our wafers are manufactured by TSMC under individually negotiated purchase orders. We do not currently have a long-term supply contract with TSMC, and therefore, TSMC is not obligated to manufacture products for us for any specified period, in any specified quantity or at any specified price, except as may be provided in a particular purchase order. Our future success depends in part on our ability to secure sufficient capacity at TSMC or other independent foundries to supply us with the wafers we require.

Most of our products are implemented using 0.13 micron and 90 nanometer process technologies on 300 millimeter wafers using process technology developed by TSMC. We currently have five separate product families in production using the 0.13 micron process. Our 72 megabit SigmaQuad and 72 megabit synchronous BurstRAM and NBT SRAM products are currently manufactured using 90 nanometer process technology. We introduced our 36 megabit SigmaQuad using 90 nanometer process technology in the quarter ended March 31, 2007. We are also developing new synchronous SRAMs using 65 nanometer process technology.

Our master die methodology enables multiple product families, and variations thereof, to be manufactured from a single mask set. As a result, based upon the way available die from a wafer are metalized, wire bonded, packaged and tested, we can create a number of different products. The manufacturing process consists of two phases, the first of which takes approximately eight to twelve weeks and results in wafers that have the potential to yield multiple products within a given product family. After the completion of this phase, the wafers are stored pending customer orders. Once we receive orders for a particular product, we perform the second phase, consisting of final wafer processing, assembly, burn-in and test, which takes approximately six to ten weeks to complete. This two-step manufacturing process enables us to significantly shorten our product lead times, providing flexibility for customization and to increase the availability of our products.

All of our manufactured wafers are tested for electrical compliance and most are packaged at Advanced Semiconductor Engineering, or ASE, which is located in Taiwan. Our test procedures require that all of our products be subjected to accelerated burn-in and extensive functional electrical testing, most of which occur at Sigurd Microelectronics Co. and King Yuan Electronics Company. We perform testing for most of our low volume products in-house at our Santa Clara, California and our Taiwan facilities.

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