Magma Design Automation (LAVA)

Evolution of the Electronic Design Automation Market

The trend toward deep submicron and system-on-chip designs has driven demand for improved electronic design automation software that enables the efficient design and implementation of these complex chips. Limitations in traditional electronic design automation technology could slow the adoption of deep submicron processes due to the difficulty in implementing designs at these small feature sizes. Historically, electronic design automation companies developed software for use by separate engineering groups to address either the front-end chip design or back-end chip implementation processes.

In the front-end design process, the chip design is conceptualized and written as a register transfer level computer program, or RTL file, that describes the required functionality of the chip. For large chips, the design is often divided into a number of individual blocks, each with its own associated RTL file. This is often done because of capacity limitations in existing electronic design automation tools. The designer also develops constraints for the design that are used to describe the desired timing performance of the chip. Finally, a target library is specified that contains detailed information about the basic functional building blocks, or logic gates, that will be used in the design. This library is typically provided by the semiconductor vendor or a third-party library vendor. The next step is to run the RTL files through synthesis software that generates a netlist. The netlist describes the circuit in terms of logic gates selected from the target library and connected such that the functionality specified in the RTL files is realized. The synthesis software also performs optimizations to attempt to meet the timing constraints specified by the designer.

A critical objective of chip design is to minimize total circuit delay, which is comprised of gate delay and wire delay. Front-end software was initially developed when the gate delay, or the time it takes for an electrical signal to travel through a logic gate, was the most significant component of total circuit delay. Wire delay, or the time it takes for a signal to travel through a wire connecting two or more gates, was negligible and designers could use simple estimates and still meet targeted circuit speeds.

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In the back-end implementation process, physical design software is used to transform the netlist generated by the front-end process into a physical layout of the chip. The resulting physical layout is usually output in a binary file format, commonly referred to as GDSII, that is used to generate the photomasks used to manufacture the integrated circuit. The two primary functions provided by traditional physical design software are placement and routing. Placement determines the optimal physical location for the logic gates on the integrated circuit. After placement is completed, routing connects the logic gates with wires to achieve the desired circuit functionality. After the layout is completed, the final step in the back-end process is to run timing analysis to verify that the chip will run at the desired circuit speed. If circuit speeds are slower than the speeds reported by the synthesis software, the design must often be iterated back through the synthesis step in an attempt to improve the timing. Since each timing closure iteration cycle can take one or more weeks, successive iterations of the design process can significantly lengthen the time it takes to design and produce new chips.

Integrated circuit (“IC”) designs which are both large and highly integrated require a fundamental new technology to create and maintain chip floorplans. Creating hierarchical chip floorplans traditionally has been a manual error-prone task with less optimal quality of results in terms of chip die area and performance. Alternative flat chip design methodologies simplify floorplan creation but suffer from a long turn around time making it unacceptable.

Deep Submicron Challenges

The trend toward deep submicron technology has rendered traditionally separate front-end and back-end electronic design automation processes less effective for rapid, cost-effective and reliable chip designs. As integrated circuits have increased in complexity and feature sizes have dropped, the problems faced by chip designers have changed. Wire delay now accounts for the majority of total circuit delay and has become the most significant factor in circuit performance for deep submicron technologies. Front-end estimates of wire delay may vary considerably from actual wire delays measured in the final layout. As a result, the front-end timing might meet the design requirements, but the final layout timing at the completion of the back-end process may be unacceptable, requiring time-consuming iterations back through the front-end process.

Deep submicron process technologies bring additional complexities to the design and implementation process that can cause chip failures. These complexities include, among others, signal integrity problems such as electrical interference from wires in close proximity, commonly referred to as crosstalk or noise, that can affect both circuit performance and functionality. Using existing design flows and software, designers must contend with analyzing and fixing these problems manually after the layout is completed. These adjustments often change the chip timing and further contribute to the timing closure problem.

These deep submicron challenges make it difficult to efficiently design chips using separate front-end and back-end processes. Semiconductor manufacturers and electronic products companies are currently seeking alternatives to older generation electronic design automation software to shorten design time, improve circuit speed, and handle larger chip designs. As a result, we believe that a significant opportunity exists for a new electronic design automation approach to chip design that can enable the design of more complex deep submicron integrated circuits, improve performance, and significantly reduce the time it takes to design and produce next-generation electronic products.

Evolution of the Electronic Design Automation Market

The trend toward deep submicron and system-on-chip designs has driven demand for improved electronic design automation software that enables the efficient design and implementation of these complex chips. Limitations in traditional electronic design automation technology could slow the adoption of deep submicron processes due to the difficulty in implementing designs at these small feature sizes. Historically, electronic design automation companies developed software for use by separate engineering groups to address either the front-end chip design or back-end chip implementation processes.

In the front-end design process, the chip design is conceptualized and written as a register transfer level computer program, or RTL file, that describes the required functionality of the chip. For large chips, the design is often divided into a number of individual blocks, each with its own associated RTL file. This is often done because of capacity limitations in existing electronic design automation tools. The designer also develops constraints for the design that are used to describe the desired timing performance of the chip. Finally, a target library is specified that contains detailed information about the basic functional building blocks, or logic gates, that will be used in the design. This library is typically provided by the semiconductor vendor or a third-party library vendor. The next step is to run the RTL files through synthesis software that generates a netlist. The netlist describes the circuit in terms of logic gates selected from the target library and connected such that the functionality specified in the RTL files is realized. The synthesis software also performs optimizations to attempt to meet the timing constraints specified by the designer.

A critical objective of chip design is to minimize total circuit delay, which is comprised of gate delay and wire delay. Front-end software was initially developed when the gate delay, or the time it takes for an electrical signal to travel through a logic gate, was the most significant component of total circuit delay. Wire delay, or the time it takes for a signal to travel through a wire connecting two or more gates, was negligible and designers could use simple estimates and still meet targeted circuit speeds.

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Table of Contents

In the back-end implementation process, physical design software is used to transform the netlist generated by the front-end process into a physical layout of the chip. The resulting physical layout is usually output in a binary file format, commonly referred to as GDSII, that is used to generate the photomasks used to manufacture the integrated circuit. The two primary functions provided by traditional physical design software are placement and routing. Placement determines the optimal physical location for the logic gates on the integrated circuit. After placement is completed, routing connects the logic gates with wires to achieve the desired circuit functionality. After the layout is completed, the final step in the back-end process is to run timing analysis to verify that the chip will run at the desired circuit speed. If circuit speeds are slower than the speeds reported by the synthesis software, the design must often be iterated back through the synthesis step in an attempt to improve the timing. Since each timing closure iteration cycle can take one or more weeks, successive iterations of the design process can significantly lengthen the time it takes to design and produce new chips.

Integrated circuit (“IC”) designs which are both large and highly integrated require a fundamental new technology to create and maintain chip floorplans. Creating hierarchical chip floorplans traditionally has been a manual error-prone task with less optimal quality of results in terms of chip die area and performance. Alternative flat chip design methodologies simplify floorplan creation but suffer from a long turn around time making it unacceptable.

Deep Submicron Challenges

The trend toward deep submicron technology has rendered traditionally separate front-end and back-end electronic design automation processes less effective for rapid, cost-effective and reliable chip designs. As integrated circuits have increased in complexity and feature sizes have dropped, the problems faced by chip designers have changed. Wire delay now accounts for the majority of total circuit delay and has become the most significant factor in circuit performance for deep submicron technologies. Front-end estimates of wire delay may vary considerably from actual wire delays measured in the final layout. As a result, the front-end timing might meet the design requirements, but the final layout timing at the completion of the back-end process may be unacceptable, requiring time-consuming iterations back through the front-end process.

Deep submicron process technologies bring additional complexities to the design and implementation process that can cause chip failures. These complexities include, among others, signal integrity problems such as electrical interference from wires in close proximity, commonly referred to as crosstalk or noise, that can affect both circuit performance and functionality. Using existing design flows and software, designers must contend with analyzing and fixing these problems manually after the layout is completed. These adjustments often change the chip timing and further contribute to the timing closure problem.

These deep submicron challenges make it difficult to efficiently design chips using separate front-end and back-end processes. Semiconductor manufacturers and electronic products companies are currently seeking alternatives to older generation electronic design automation software to shorten design time, improve circuit speed, and handle larger chip designs. As a result, we believe that a significant opportunity exists for a new electronic design automation approach to chip design that can enable the design of more complex deep submicron integrated circuits, improve performance, and significantly reduce the time it takes to design and produce next-generation electronic products.

Evolution of the Electronic Design Automation Market

The trend toward deep submicron and system-on-chip designs has driven demand for improved electronic design automation software that enables the efficient design and implementation of these complex chips. Limitations in traditional electronic design automation technology could slow the adoption of deep submicron processes due to the difficulty in implementing designs at these small feature sizes. Historically, electronic design automation companies developed software for use by separate engineering groups to address either the front-end chip design or back-end chip implementation processes.

In the front-end design process, the chip design is conceptualized and written as a register transfer level computer program, or RTL file, that describes the required functionality of the chip. For large chips, the design is often divided into a number of individual blocks, each with its own associated RTL file. This is often done because of capacity limitations in existing electronic design automation tools. The designer also develops constraints for the design that are used to describe the desired timing performance of the chip. Finally, a target library is specified that contains detailed information about the basic functional building blocks, or logic gates, that will be used in the design. This library is typically provided by the semiconductor vendor or a third-party library vendor. The next step is to run the RTL files through synthesis software that generates a netlist. The netlist describes the circuit in terms of logic gates selected from the target library and connected such that the functionality specified in the RTL files is realized. The synthesis software also performs optimizations to attempt to meet the timing constraints specified by the designer.

A critical objective of chip design is to minimize total circuit delay, which is comprised of gate delay and wire delay. Front-end software was initially developed when the gate delay, or the time it takes for an electrical signal to travel through a logic gate, was the most significant component of total circuit delay. Wire delay, or the time it takes for a signal to travel through a wire connecting two or more gates, was negligible and designers could use simple estimates and still meet targeted circuit speeds.

In the back-end implementation process, physical design software is used to transform the netlist generated by the front-end process into a physical layout of the chip. The resulting physical layout is usually output in a binary file format, commonly referred to as GDSII, that is used to generate the photomasks used to manufacture the integrated circuit. The two primary functions provided by traditional physical design software are placement

2

Table of Contents

and routing. Placement determines the optimal physical location for the logic gates on the integrated circuit. After placement is completed, routing connects the logic gates with wires to achieve the desired circuit functionality. After the layout is completed, the final step in the back-end process is to run timing analysis to verify that the chip will run at the desired circuit speed. If circuit speeds are slower than the speeds reported by the synthesis software, the design must often be iterated back through the synthesis step in an attempt to improve the timing. Since each timing closure iteration cycle can take one or more weeks, successive iterations of the design process can significantly lengthen the time it takes to design and produce new chips.

Highly integrated, large integrated circuit (“IC”) designs require a fundamental new technology to create and maintain chip floorplans. Today, creating hierarchical chip floorplans is a manual error-prone task with less optimal quality of results in terms of chip die area and performance. Alternative flat chip design methodologies simplify floorplan creation but suffer from a long turn around time making it unacceptable.

Deep Submicron Challenges

The trend toward deep submicron technology has rendered traditionally separate front-end and back-end electronic design automation processes less effective for rapid, cost-effective and reliable chip designs. As integrated circuits have increased in complexity and feature sizes have dropped, the problems faced by chip designers have changed. Wire delay now accounts for the majority of total circuit delay and has become the most significant factor in circuit performance for deep submicron technologies. Front-end estimates of wire delay may vary considerably from actual wire delays measured in the final layout. As a result, the front-end timing might meet the design requirements, but the final layout timing at the completion of the back-end process may be unacceptable, requiring time-consuming iterations back through the front-end process.

Deep submicron process technologies bring additional complexities to the design and implementation process that can cause chip failures. These include signal integrity problems such as electrical interference from wires in close proximity, commonly referred to as crosstalk or noise, that can affect both circuit performance and functionality. Using existing design flows and software, designers must contend with analyzing and fixing these problems manually after the layout is completed. These adjustments often change the chip timing and further contribute to the timing closure problem.

These deep submicron challenges make it difficult to efficiently design chips using separate front-end and back-end processes. Semiconductor manufacturers and electronic products companies are currently seeking alternatives to older generation electronic design automation software to shorten design time, improve circuit speed, and handle larger chip designs. As a result, a significant opportunity exists for a new electronic design automation approach to chip design that can enable the design of more complex deep submicron integrated circuits, improve performance, and significantly reduce the time it takes to design and produce next-generation electronic products.

Evolution of the Electronic Design Automation Market

The trend toward deep submicron and system-on-chip designs has driven demand for improved electronic design automation software that enables the efficient design and implementation of these complex chips. Limitations in traditional electronic design automation technology could slow the adoption of deep submicron processes due to the difficulty in implementing designs at these small feature sizes. Historically, electronic design automation companies developed software for use by separate engineering groups to address either the front-end chip design or back-end chip implementation processes.

In the front-end design process, the chip design is conceptualized and written as a register transfer level computer program, or RTL file, that describes the required functionality of the chip. For large chips, the design is often divided into a number of individual blocks, each with its own associated RTL file. This is often done because of capacity limitations in existing electronic design automation tools. The designer also develops constraints for the design that are used to describe the desired timing performance of the chip. Finally, a target library is specified that contains detailed information about the basic functional building blocks, or logic gates, that will be used in the design. This library is typically provided by the semiconductor vendor or a third-party library vendor. The next step is to run the RTL files through synthesis software that generates a netlist. The netlist describes the circuit in terms of logic gates selected from the target library and connected such that the functionality specified in the RTL files is realized. The synthesis software also performs optimizations to attempt to meet the timing constraints specified by the designer.

A critical objective of chip design is to minimize total circuit delay, which is comprised of gate delay and wire delay. Front-end software was initially developed when the gate delay, or the time it takes for an electrical signal to travel through a logic gate, was the most significant component of total circuit delay. Wire delay, or the time it takes for a signal to travel through a wire connecting two or more gates, was negligible and designers could use simple estimates and still meet targeted circuit speeds.

In the back-end implementation process, physical design software is used to transform the netlist generated by the front-end process into a physical layout of the chip. The resulting physical layout is usually output in a binary file format, commonly referred to as GDSII, that is used to generate the photomasks used to manufacture the integrated circuit. The two primary functions provided by traditional physical design software are placement

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Table of Contents

and routing. Placement determines the optimal physical location for the logic gates on the integrated circuit. After placement is completed, routing connects the logic gates with wires to achieve the desired circuit functionality. After the layout is completed, the final step in the back-end process is to run timing analysis to verify that the chip will run at the desired circuit speed. If circuit speeds are slower than the speeds reported by the synthesis software, the design must often be iterated back through the synthesis step in an attempt to improve the timing. Since each timing closure iteration cycle can take one or more weeks, successive iterations of the design process can significantly lengthen the time it takes to design and produce new chips.

Highly integrated, large integrated circuit (“IC”) designs require a fundamental new technology to create and maintain chip floorplans. Today, creating hierarchical chip floorplans is a manual error-prone task with less optimal quality of results in terms of chip die area and performance. Alternative flat chip design methodologies simplify floorplan creation but suffer from a long turn around time making it unacceptable.

Deep Submicron Challenges

The trend toward deep submicron technology has rendered traditionally separate front-end and back-end electronic design automation processes less effective for rapid, cost-effective and reliable chip designs. As integrated circuits have increased in complexity and feature sizes have dropped, the problems faced by chip designers have changed. Wire delay now accounts for the majority of total circuit delay and has become the most significant factor in circuit performance for deep submicron technologies. Front-end estimates of wire delay may vary considerably from actual wire delays measured in the final layout. As a result, the front-end timing might meet the design requirements, but the final layout timing at the completion of the back-end process may be unacceptable, requiring time-consuming iterations back through the front-end process.

Deep submicron process technologies bring additional complexities to the design and implementation process that can cause chip failures. These include signal integrity problems such as electrical interference from wires in close proximity, commonly referred to as crosstalk or noise, that can affect both circuit performance and functionality. Using existing design flows and software, designers must contend with analyzing and fixing these problems manually after the layout is completed. These adjustments often change the chip timing and further contribute to the timing closure problem.

These deep submicron challenges make it difficult to efficiently design chips using separate front-end and back-end processes. Semiconductor manufacturers and electronic products companies are currently seeking alternatives to older generation electronic design automation software to shorten design time, improve circuit speed, and handle larger chip designs. As a result, a significant opportunity exists for a new electronic design automation approach to chip design that can enable the design of more complex deep submicron integrated circuits, improve performance, and significantly reduce the time it takes to design and produce next-generation electronic products.

Evolution of the Electronic Design Automation Market

The trend toward deep submicron and system-on-chip designs has driven demand for improved electronic design automation software that enables the efficient design and implementation of these complex chips. Limitations in traditional electronic design automation technology could slow the adoption of deep submicron processes due to the difficulty in implementing designs at these small feature sizes. Historically, electronic design automation companies developed software for use by separate engineering groups to address either the front-end chip design or back-end chip implementation processes.

In the front-end design process, the chip design is conceptualized and written as a register transfer level computer program, or RTL file, that describes the required functionality of the chip. For large chips, the design is often divided into a number of individual blocks, each with its own associated RTL file. This is often done because of capacity limitations in existing electronic design automation tools. The designer also develops constraints for the design that are used to describe the desired timing performance of the chip. Finally, a target library is specified that contains detailed information about the basic functional building blocks, or logic gates, that will be used in the design. This library is typically provided by the semiconductor vendor or a third-party library vendor. The next step is to run the RTL files through synthesis software that generates a netlist. The netlist describes the circuit in terms of logic gates selected from the target library and connected such that the functionality specified in the RTL files is realized. The synthesis software also performs optimizations to attempt to meet the timing constraints specified by the designer.

A critical objective of chip design is to minimize total circuit delay, which is comprised of gate delay and wire delay. Front-end software was initially developed when the gate delay, or the time it takes for an electrical signal to travel through a logic gate, was the most significant component of total circuit delay. Wire delay, or the time it takes for a signal to travel through a wire connecting two or more gates, was negligible and designers could use simple estimates and still meet targeted circuit speeds.

In the back-end implementation process, physical design software is used to transform the netlist generated by the front-end process into a physical layout of the chip. The resulting physical layout is usually output in a binary file format, commonly referred to as GDSII, that is used to generate the photomasks used to manufacture the integrated circuit. The two primary functions provided by traditional physical design software are placement and routing. Placement determines the optimal physical location for the logic gates on the integrated circuit. After placement is completed, routing connects the logic gates with wires to achieve the desired circuit

2

Table of Contents

functionality. After the layout is completed, the final step in the back-end process is to run timing analysis to verify that the chip will run at the desired circuit speed. If circuit speeds are slower than the speeds reported by the synthesis software, the design must often be iterated back through the synthesis step in an attempt to improve the timing. Since each timing closure iteration cycle can take one or more weeks, successive iterations of the design process can significantly lengthen the time it takes to design and produce new chips.

Deep Submicron Challenges

The trend toward deep submicron technology has rendered traditionally separate front-end and back-end electronic design automation processes less effective for rapid, cost-effective and reliable chip designs. As integrated circuits have increased in complexity and feature sizes have dropped, the problems faced by chip designers have changed. Wire delay now accounts for the majority of total circuit delay and has become the most significant factor in circuit performance for deep submicron technologies. Front-end estimates of wire delay may vary considerably from actual wire delays measured in the final layout. As a result, the front-end timing might meet the design requirements, but the final layout timing at the completion of the back-end process may be unacceptable, requiring time-consuming iterations back through the front-end process.

Deep submicron process technologies bring additional complexities to the design and implementation process that can cause chip failures. These include signal integrity problems such as electrical interference from wires in close proximity, commonly referred to as crosstalk or noise, that can affect both circuit performance and functionality. Using existing design flows and software, designers must contend with analyzing and fixing these problems manually after the layout is completed. These adjustments often change the chip timing and further contribute to the timing closure problem.

These deep submicron challenges make it difficult to efficiently design chips using separate front-end and back-end processes. Semiconductor manufacturers and electronic products companies are currently seeking alternatives to older generation electronic design automation software to shorten design time, improve circuit speed, and handle larger chip designs. As a result, a significant opportunity exists for a new electronic design automation approach to chip design that can enable the design of more complex deep submicron integrated circuits, improve performance, and significantly reduce the time it takes to design and produce next-generation electronic products.