SNPS » Topics » Verification Group

This excerpt taken from the SNPS 10-K filed Jan 12, 2006.

Verification Group

Our Verification Group is responsible for our Discovery Verification platform, which combines our simulation and verification products and design-for-verification methodologies, and provides a consistent control environment to help significantly improve the speed, breadth and accuracy of our customers’ verification efforts.

The following are the Discovery Verification platform’s principal products and solutions:

·       VCS® comprehensive RTL verification solution, which includes technologies that support model development, testbench creation, coverage feedback and debugging techniques.

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·       Vera® testbench generator, which automates the creation of testbenches, custom models that provide simulation inputs and respond to simulated outputs from the design during verification. Automating this process significantly improves verification quality.

·       NanoSim® FastSPICE circuit simulation product for analog, mixed signal and digital IC verification, which offers high performance and capacity for pre-and-post-layout full-chip circuit simulation, timing and power analysis.

·       HSIM® hierarchical FastSPICE circuit simulation product for analog, mixed-signal and digital IC verification, which offers pre and post-layout full-chip circuit simulation and memory verification.

·       HSPICE® circuit simulator, which offers high-accuracy, transistor-level circuit simulation, thereby enabling designers to better predict the timing, power consumption, functionality and analog performance of their designs.

·       Verification IP reusable IP designed to test specific functions and adherence to industry protocols in an IC design, which we believe is becoming increasingly important to more quickly achieving verification sign-off.

·       Discovery AMS mixed-signal verification solution which is based on the VCS, NanoSim and HSPICE simulators.

The Verification Group also develops and markets tools that perform system level design, design rule checking and hybrid formal verification, specialized functions that designers often require during verification.

This excerpt taken from the SNPS 10-K filed Jan 12, 2005.

Verification Group

        Discovery Verification Platform.    Our Discovery Verification Platform includes our verification and simulation products. The increasing size and complexity of today's ICs and SoCs have vastly increased the time and effort required to verify chip designs, with verification estimated to consume 60% to 70% of total design time. As a result, reducing verification "risk" (i.e. minimizing the possibility of finding design "bugs" when the ICs are delivered from the foundry) has become increasingly important to customers. To manage and reduce this verification risk, our Discovery platform combines our simulation and verification products and design-for-verification methodologies, and provides a consistent control environment to significantly improve the speed, breadth and accuracy of our customers' verification efforts.

        Our Discovery Verification Platform includes the following principal products:

    VCS® functional verification product, the engine of the Discovery Verification Platform and often used in simulation "farms" consisting of hundreds of computers. The VCS product includes technologies that support model development, testbench creation, coverage feedback and debugging techniques. Our fiscal 2004 release of the VCS product expands support of our Vera® product, making testbench automation native to VCS, and helping post a two to five times improvement in runtime.

    System Studio system level design product focused on system-level algorithm and architecture design and analysis, as well as the interaction between software and hardware and permits designers to model various architectural alternatives for their chips at a system level.

    Vera® testbench generator, which automates the creation of testbenches, custom models that provide simulation inputs and respond to simulated outputs from the design during verification. Automating this process significantly improves verification quality. The 2004 release of the Vera product is up to 10 times faster than its predecessor and is also available native to the VCS product, providing increased productivity benefits.

    LEDA® design rule checker, which enhances a designer's ability to check a design to ensure it can be for synthesized, simulated, tested and reused.

    Formality® formal verification solution, which compares two versions of a design to determine if they are equivalent. The use of formal verification reduces the need to perform functional verification, which is substantially more time-consuming, thus potentially saving a significant amount of time in the overall design process.

    Magellan™ hybrid formal verification product, which combines functional and formal verification technologies to allow engineers to find deep, corner-case design defects during verification.

    NanoSim® simulation and analysis product for analog and mixed signal verification, which offers circuit simulation, timing and power analysis in a single solution. The NanoSim product is a key component of our Discovery AMS verification solution.

    HSPICE® circuit simulator, which offers high-accuracy, transistor-level circuit simulation, thereby enabling designers to better predict the timing, power consumption and functionality of their designs. During fiscal 2004, we announced enhancements to the HSPICE tool resulting in significant improvements in performance and support for high-frequency and RF IC designs.

    Verification IP reusable IP that are designed to test specific functions and adherence to industry protocols in an IC design, which we believe is becoming increasingly important to more quickly achieving verification sign-off.

        In fiscal 2004, we delivered the Discovery AMS solution, a subset of our verification technologies optimized to perform verification on analog and mixed signal designs.

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EXCERPTS ON THIS PAGE:

10-K
Jan 12, 2006
10-K
Jan 12, 2005
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